A 16kb lTlC FeRAM Testchip Using Current-Based Reference Scheme

A 16kb lTlC FeRAM testchip is designed and fabricated in a 0.35pm FeRAM process. The testchip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the lTlC cell with 2T2C robustness to fatigue. The testchip achieves an access time of 6211s at 3V. Introduction Reference generation is an essential component of lT lC Ferroelectric Random Access Memory (FeRAM) design. The conventional approach of using a fixed reference voltage (V,,f) for the entire memory array [ l ] does not track the ferroelectric process variation across the chip, nor the ferroelectric-materia1 degradation with time. On the other hand, generating a V,f separately for each column of the memory array at the time of data retrieval [2][3] reduces the effect of process variation on the sensing signal but fatigues reference cells at a rate different from that of memory cells [3]. This paper presents measurement results from a 256x64bit lT lC FeRAM testchip that features: 1) a reference scheme that balances the fatigue effect evenly between the memory cells and the reference cells by generating a reference current (Iref) and sharing it with a row (instead of a column) of memory cells, and 2) a current-steering sense amplifier implementing this scheme. The testchip has been designed and fabricated in a 0.35pm CMOS process with added planar ferroelectric capacitors. Reference Generation Fig. 1 compares two reference schemes: one using a reference cell per column and the other using a reference cell per row of the memory array. Assuming a total of n rows being accessed sequentially, the reference row at the bottom of the array will be accessed, and hence fatigued, n times more than a typical memory row. On the other hand, a reference cell per row of the memory cell is accessed at exactly the same rate as the memory cells, and hence is fatigued at exactly the same rate. This is expected to increase the ITlC FeRAM lifetime by the same factor n. Fig. 2 shows an implementation of a reference column pair, RBL and m, in association with a set of eight memory columns. RBL and RBL are each connected to a memory cell, one of which always stores a “1” and the other a “0”. The voltage developed on a typical BL, VI for a stored “l”, and V, for a stored “O”, will be identical to those of RBL and RBL, independent of the access rate of memory cells, since they all share the same WL and PL. The voltage developed on BL (VJ, RBL (V,), and RBL (V,), are converted by a set of -